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rev. prj 27/02/02 preliminary t echnical data preliminary technical data information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7450 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-470 0 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 differential input, 1msps, 12-bit adc in so-8 and s0-8 features fast throughput rate: 1msps specified for v dd of 3 v and 5 v low power at max throughput rate: 3 mw typ at 833ksps with 3 v supplies 8 mw typ at 1msps with 5 v supplies fully differential analog input wide input bandwidth: 70db sinad at 300khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface - spi tm /qspi tm / microwire tm / dsp compatible powerdown mode: 1a max 8 pin soic and soic packages applications transducer interface battery powered systems data acquisition systems portable instrumentation motor control communications general description the ad7450 is a 12-bit, high speed, low power, succes- sive-approximation (sar) analog-to-digital converter featuring a fully differential analog input. it operates from a single 3 v or 5 v power supply and features throughput rates up to 833ksps or 1msps respectively. this part contains a low-noise, wide bandwidth, differen- tial track and hold amplifier (t/h) which can handle input frequencies in excess of 1mhz with the -3db point being 20mhz typically. the reference voltage for the ad7450 is applied externally to the v ref pin and can be varied from 100 mv to 2.5 v depending on the power supply and to suit the application. the value of the refer- ence voltage determines the common mode voltage range of the part. with this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points. the conversion process and data acquisition are controlled using cs and the serial clock allowing the device to inter- face with microprocessors or dsps. the input signals are sampled on the falling edge of cs and the conversion is also initiated at this point. functional block diagram the sar architecture of this part ensures that there are no pipeline delays. the ad7450 uses advanced design techniques to achieve very low power dissipation at high throughput rates. product highlights 1.operation with either 3 v or 5 v power supplies. 2.high throughput with low power consumption. with a 3v supply, the ad7450 offers 3mw typ power consumption for 833ksps throughput. 3.fully differential analog input. 4.flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. this part also features a shutdown mode to maximize power efficiency at lower throughput rates. 5.variable voltage reference input. 6.no pipeline delay. 7.accurate control of the sampling instant via a cs input and once off conversion control. 8. enob > 8 bits typ with 100mv reference . microwire is a trademark of national semiconductor corporation. spi and qspi are trademarks of motorola, inc. 12-bit successive approximation adc control logic ad7450 v in+ v in- v ref gnd sclk sdata cs v dd t/h
rev. prj preliminary technical data C2C parameter a version 1 b version 1 units test conditions/comments dynamic performance f in = 300khz sine wave, f sample = 833ksps, 1msps signal to (noise + distortion) ratio 70 70 db min (sinad) 2 total harmonic distortion (thd) 2 -80 -80 db max peak harmonic or spurious noise 2 -80 -80 db max intermodulation distortion (imd) 2 second order terms -78 -78 db typ third order terms -78 -78 db typ aperture delay 3 10 10 ns typ aperture jitter 3 50 50 ps typ full power bandwidth 3 20 20 mhz typ @ -3 db 2.5 2.5 mhz typ @ -0.1 db common mode rejection ratio tbd tbd db (cmrr) 2 dc accuracy resolution 12 12 bits integral nonlinearity (inl) 2 2 1 lsb max differential nonlinearity (dnl) 2 1 1 lsb max guaranteed no missed codes to 12 bits. zero code error 2 5 5 lsb max positive gain error 2 5 5 lsb max negative gain error 2 5 5 lsb max analog input full scale input span v in+ - v in - volts 2 x v ref 4 absolute input voltage v in+ v cm 3 v ref /2 volts v cm = v ref v in- v cm 3 v ref /2 volts v cm = v ref dc leakage current 1 1 a max input capacitance 20 20 pf typ when in track 5 5 pf typ when in hold reference input v ref input voltage 2.5 5 2.5 volts 5 v supply (1% tolerance for specified performance) 1.25 6 1.25 volts 3 v supply (1% tolerance for specified performance) dc leakage current 1 1 a max v ref input capacitance 15 15 pf typ logic inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current, i in 1 1 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 7 10 10 pf max logic outputs output high voltage, v oh 2.8 2.8 v min i source = 200a output low voltage, v ol 0.4 0.4 v max i sink =200a floating-state leakage current 10 10 a max floating-state output capacitance 7 10 10 pf max output coding twos complement conversion rate conversion time 16 16 sclk cycles 888ns with an 18mhz sclk 1.07s with a 15mhz sclk track/hold acquisition time 8 275 275 ns max sine wave input throughput rate 9 1 1 msps max @ v dd = 5v 833 833 ksps max @ v dd = 3v ad7450 - specifications 1 ( v dd = 2.7v to 3.3v, f sclk = 15mhz, f s = 833khz, v ref = 1.25 v; v dd = 4.75v to 5.25v, f sclk = 18mhz, f s = 1mhz, v ref = 2.5 v; v cm 3 = v ref ; t a = t min to t max , unless otherwise noted.)
rev. prj preliminary technical data C3C limit at t min , t max parameter +3v +5v units description f sclk 4 10 10 khz min 15 18 mhz max t convert 16 x t sclk 16 x t sclk t sclk = 1/f sclk 1.07 0.88 s max sclk = 15mhz, 18mhz t quiet 50 50 ns min minimum quiet time between the end of a serial read and the next falling edge of cs t 1 10 10 ns min minimum cs pulsewidth t 2 10 10 ns min cs falling edge to sclk falling edge setup time t 3 5 20 20 ns max delay from cs falling edge until sdata 3-state disabled t 4 5 40 40 ns max data access time after sclk falling edge t 5 0.4 t sclk 0.4 t sclk ns min sclk high pulse width t 6 0.4 t sclk 0.4 t sclk ns min sclk low pulse width t 7 10 10 ns min sclk edge to data valid hold time t 8 6 10 10 ns min sclk falling edge to sdata 3-state enabled 45 45 ns max sclk falling edge to sdata 3-state enabled t power-up 7 tbd tbd s max power-up time from full power-down notes 1 sample tested at +25c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 volts. 2 see figure 1 and the serial interface section. 3 common mode voltage. 4 mark/space ratio for the sclk input is 40/60 to 60/40. 5 measured with the load circuit of figure 2 and defined as the time required for the output to cross 0.8 v or 2.4 v with v dd = 5 v and time for an output to cross 0.4 v or 2.0 v for v dd = 3 v. 6 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 2. the meas ured num- ber is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 see power-up time section. specifications subject to change without notice. parameter a version 1 b version 1 units test conditions/comments power requirements v dd 3/5 3/5 vmin/max range: 3 v 10%; 5 v 5% i dd 8,10 normal mode(static) 1 1 ma typ v dd =3 v/5 v. sclk on or off normal mode (operational) 2.6 2.6 ma max v dd = 5 v. f sample =1msps 2 2 ma max v dd = 3 v. f sample =833ksps full power-down mode 1 1 a max sclk on or off power dissipation normal mode (operational) 13 13 mw max v dd =5 v. f sample =1msps 6 6 mw max v dd =3 v. f sample =833ksps full power-down 5 5 w max v dd =5 v. sclk on or off 3 3 w max v dd =3 v. sclk on or off ad7450 - timing specifications 1,2 ( v dd = 2.7v to 3.3v, f sclk = 15mhz, f s = 833khz, v ref = 1.25 v; v dd = 4.75v to 5.25v, f sclk = 18mhz, f s = 1mhz, v ref = 2.5 v; v cm 3 = v ref ; t a = t min to t max , unless otherwise noted.) ad7450 notes 1 temperature ranges as follows: a, b versions: C40c to +85c. 2 see terminology section. 3 common mode voltage. the input signal can be centered on any choice of dc common mode voltage as long as this value is in the range specified in figure 8. 4 because the input span of v in+ and v in- are both v ref , and they are 180 out of phase, the differential voltage is 2 x v ref . 5 the reference is functional from 100mv and for 5v supplies it can range up to tbdv (see reference section). 6 the reference is functional from 100mv and for 3v supplies it can range up to 2.2v (see reference section). 7 sample tested @ +25c to ensure compliance. 8 see power versus throughput rate section. 8 t convert + t quiet (see serial interface section) 10 measured with a midscale dc input. specifications subject to change without notice.
rev. prj preliminary technical data C4C ad7450 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7450 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +7 v v in+ to gnd . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v v in- to gnd . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v digital input voltage to gnd . . . -0.3 v to v dd + 0.3 v digital output voltage to gnd . . -0.3 v to v dd + 0.3 v v ref to gnd . . . . . . . . . . . . . . . . . . . -0.3 v to v dd +0.3 v input current to any pin except supplies 2 . . . . 10ma operating temperature range commercial (a, b version) . . . . . . . . . -40 o c to +85 o c storage temperature range . . . . . . . . . -65 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . +150 o c soic, soic package, power dissipation . . . . 450mw u ja thermal impedance . . . . . . . . . . 157 c/w (soic) 205.9c/w (soic) u jc thermal impedance . . . . . . . . . . . 56c/w (soic) 43.74c/w (soic) lead temperature, soldering vapor phase (60 secs) . . . . . . . . . . . . . . . . . . . +215 o c infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . +220 o c e s d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t b d linearity package model range error (lsb) 1 option 4 branding information ad7450ar -40c to +85c 2 lsb so-8 ad7450ar ad7450arm -40c to +85c 2 lsb rm-8 cpa ad7450br -40c to +85c 1 lsb so-8 ad7450br ad7450brm -40c to +85c 1 lsb rm-8 cpb eval-ad7450cb 2 evaluation board eval-control brd2 3 controller board ordering guide notes 1 linearity error here refers to integral linearity error. 2 this can be used as a stand-alone evaluation board or in conjunction with the evaluation board controller for evaluation/demons tration purposes. 3 evaluation board controller. this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. 4 s0 = soic; rm = soic notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up. figure 1. serial interface timing diagram figure 2. load circuit for digital output timing specifications 1 2345 13 16 15 14 t 3 0 0 0 0 db11 db10 db2 db1 db0 t 2 4 leading zeros 3-state t 4 t 6 t 5 t 7 t 8 t quiet convert t b c s sclk s data t 1 +1.6v i ol 200a 200a i oh to ou tp ut pin c l 50 pf
rev. prj preliminary technical data C5C ad7450 pin configuration soic and soic pin function description pin no. pin mnemonic function 1v ref reference input for the ad7450. an external reference must be applied to this input. for a 5 v power supply, the reference is 2.5 v (1%) and for a 3 v power supply, the reference is 1.25 v (1%) for specified performance. this pin should be decoupled to gnd with a capacitor of at least 0.1f. see the reference section for more details. 2v in+ positive terminal for differential analog input. 3v in- negative terminal for differential analog input. 4 g n d analog ground. ground reference point for all circuitry on the ad7450. all analog input signals and any external reference signal should be referred to this gnd voltage. 5 cs chip select. active low logic input. this input provides the dual function of initiating a conversion on the ad7450 and framing the serial data transfer. 6 sdata serial data. logic output. the conversion result from the ad7450 is provided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream consists of four leading zeros followed by the 12 bits of conversion data which are provided msb first. the output coding is twos complement. 7 sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the ad7450's conversion process. 8v dd power supply input. v dd is 3 v (10%) or 5 v (5%). this supply should be decoupled to gnd with a 0.1f capacitor and a 10f tantalum capacitor. ad7450 (not to scale) top view 1 2 3 4 5 6 7 8 v ref v in+ v in- gnd cs sdata sclk v dd
rev. prj preliminary technical data C6C ad7450 terminology signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit con- verter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7450, it is defined as: thd (db ) = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second to the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms in- clude (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the ad7450 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual dis- tortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. aperture delay this is the amount of time from the leading edge of the sampling clock until the adc actually takes the sample. aperture jitter this is the sample to sample variation in the effective point in time at which the actual sample is taken. full power bandwidth the full power bandwidth of an adc is that input fre- quency at which the amplitude of the reconstructed fundamental is reduced by 0.1db or 3db for a full scale input. common mode rejection ratio (cmrr) the common mode rejection ratio is defined as the ratio of the power in the adc output at full-scale fre- quency, f, to the power of a 200mv p-p sine wave applied to the common mode voltage of v in+ and v in- of fre- quency fs: cmrr (db) = 10log(pf/pfs) pf is the power at the frequncy f in the adc output; pfs is the power at frequency fs in the adc output. integral nonlinearity (inl) this is the maximum deviation from a straight line pass- ing through the endpoints of the adc transfer function. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero code error this is the deviation of the midscale code transition (111...111 to 000...000) from the ideal v in+ -v in - (i.e., 0lsb). positive gain error this is the deviation of the last code transition (011...110 to 011...111) from the ideal v in+ -v in- (i.e., +v ref - 1lsb), after the zero code error has been adjusted out. negative gain error this is the deviation of the first code transition (100...000 to 100...001) from the ideal v in+ -v in - (i.e., -v ref + 1lsb), after the zero code error has been adjusted out. track/hold acquisition time the track/hold amplifier returns into track mode on the 13th sclk rising edge (see the serial interface sec- tion). the track/hold acquisition time is the minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal. power supply rejection (psr) the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 200mv p-p sine wave applied to the adc v dd supply of frequency fs. psrr (db) = 10 log (pf/pfs) pf is the power at frequency f in the adc output; pfs is the power at frequency fs in the adc output.
rev. prj preliminary technical data C7C ad7450 performance curves tpc 1 and tpc 2 show the typical fft plots for the ad7450 with v dd of 5v and 3v, 1mhz and 833khz sam- pling frequency respectively and an input frequency of 300khz. -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 300 350 400 450 500 frequency (khz) snr (dbs) 8192 point fft fsample = 1msps fin = 300khz sinad = 71.7db thd = -82.8db sfdr = -85.3db tpc 1. ad7450 dynamic performance at 1msps with v dd =5v -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 300 350 frequency (khz) snr (dbs) 8192 point fft f sample = 833ksps f in = 300khz sinad = 70.2db thd = -86db sfdr = -87.1db tpc 2. ad7450 dynamic performance at 833ksps with v dd = 3v tpc 3 shows the signal-to-(noise+distortion) ratio performance versus the analog input frequency for various supply voltages while sampling at 1msps (v dd = 5v5%) and 833ksps (v dd = 3v10%). title 0 0 0 00 0 t it le 0000 tpc 3. sinad vs analog input frequency for various supply voltages tbd tpc 4 shows the power supply rejection ratio versus supply ripple frequency for the ad7450. here, a 200mv p-p sine wave is coupled onto the v dd supply. a 10nf decoupling capacitor was used on the supply and a 1f decoupling capacitor was used on v ref . title 0 0 0 00 0 t it l e 0000 tpc 4. power supply rejection (see terminology sec- tion) vs. supply ripple frequency at 5v and 3v tbd
rev. prj preliminary technical data C8C ad7450 tpc 5 and tpc 6 show typical dnl plots for the ad7450 with v dd of 5v and 3v, 1mhz and 833khz sampling frequency respectively and an input frequency of 300khz. -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 code dnl error ( lsb ) tpc 5 typical differential nonlinearity (dnl) v dd = 5v -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 code dnl error ( lsb ) tpc 6 typical differential nonlinearity (dnl) v dd = 3v tpc 7 and tpc 8 show typical inl plots for the ad7450 with v dd of 5v and 3v, 1mhz and 833khz sampling frequency respectively and an input frequency of 300khz. -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 code inl error ( lsb ) tpc 7 typical integral nonlinearity (inl) v dd = 5v -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 code inl error ( lsb ) tpc 8 typical integral nonlinearity (inl) v dd = 3v
rev. prj preliminary technical data C9C ad7450 tpc 9 and tpc 10 show the change in dnl versus v ref for v dd of 5v and 3.3v respectively. -1 -0.5 0 0.5 1 00.511.522.5 vref chan g e in dnl positive dnl negative dnl tpc 9.change in dnl vs reference voltage v dd = 5v -1 -0.5 0 0.5 1 1.5 0 0.6 1.2 1.8 2.4 vref chan g e in dnl positive dnl negative dnl tpc 10. change in dnl vs reference voltage v dd = 3.3v* tpc 11 and tpc 12 show the change in inl versus v ref for v dd of 5v and 3.3v respectively. -1.5 -1 -0.5 0 0.5 1 1.5 00.511.522.5 vref chan g e in inl positive inl negative inl tpc 11. change in inl vs reference voltage v dd = 5v -1.5 -1 -0.5 0 0.5 1 1.5 2 0 0.6 1.2 1.8 2.4 vref chan g e in inl positive inl negative inl tpc 12. change in inl vs reference voltage v dd = 3.3v* *see reference section
rev. prj preliminary technical data C10C ad7450 tpc 13 shows the change in zero code error versus the reference voltage for v dd = 5v and 3.3v. -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 0.25 0.75 1.25 1.75 2.25 vref zero code error ( lsb ) 2.5 vdd = 5 v fs = 1msps vdd = 3.3 v fs = 833ksps tpc 13. change in zero code error vs reference voltage v dd = 5v and 3.3 v* tpc 14 shows a histogram plot for 10000 conversions of a dc input using the ad7450 with v dd = 5v. both ana- log inputs were set to v ref , which is the center of the code transition. 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 2044 2045 2046 2047 2048 2049 code 10000 codes tpc 14. histogram of 10000 conversions of a dc input with v dd = 5v tpc 15 shows a histogram plot for 10000 conversions of a dc input for v dd of 3v. as in tpc 14, both inputs are set to v ref . both plots indicate good noise performance as the majority of codes appear in one output bin. 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 2044 2045 2046 2047 2048 2049 code 71 codes 9839 codes 90 codes tpc 15. histogram of 10000 conversions of a dc input with v dd = 3v tpc 16 shows the effective number of bits (enob) versus the reference voltage for v dd 5v and 3.3v. note that the ad7450 has an enob of greater than 8-bits typi- cally when v ref = 100mv. 6 7 8 9 10 11 12 00.511.522.5 vref effective number of bits vdd = 5v fs = 1msps vdd = 3.3v fs = 833ksps tpc 16. change in enob vs reference voltage v dd = 5v and 3.3 v* *see reference section.
rev. prj preliminary technical data C11C ad7450 tpc 17 shows the common mode rejection ratio versus supply ripple frequency for the ad7450 for both v dd = 5v and 3 v. here a 200mv p-p sine wave is coupled onto the common mode voltage of v in+ and v in- . 0 10 20 30 40 50 60 70 80 90 10 100 1000 10000 frequency (khz) cmrr ( db ) vdd = 5 v vdd = 3 v tpc 17. cmrr versus frequency for v dd = 5v and 3 v circuit information the ad7450 is a fast, low power, single supply, 12-bit successive approximation analog-to-digital converter (adc). it can operate with a 5 v and 3v power supply and is capable of throughput rates up to 1msps and 833ksps when supplied with a 18mhz or 15mhz clock respectively. this part requires an external reference to be applied to the v ref pin, with the value of the reference chosen depending on the power supply and to suit the application. when operated with a 5 v supply, the maximum reference that can be applied to the part is 2.5 v and when operated with a 3 v supply, the maximum reference that can be applied to the part is 2.2 v. (see reference section). the ad7450 has an on-chip differential track and hold amplifier, a successive approximation (sar) adc and a serial interface, housed in either an 8-lead soic or soic package. the serial clock input accesses data from the part and also provides the clock source for the successive-approximation adc. the ad7450 features a power-down option for reduced power consumption be- tween conversions. the power-down feature is implemented across the standard serial interface as de- scribed in the modes of operation section. converter operation the ad7450 is a successive approximation adc based around two capacitive dacs. figures 3 and 4 show sim- plified schematics of the adc in acquisition and conversion phase respectively. the adc comprises of control logic, a sar and two capacitive dacs. in figure 3 (acquisition phase), sw3 is closed and sw1 and sw2 are in position a, the comparator is held in a bal- anced condition and the sampling capacitor arrays acquire the differential signal on the input. sw3 v in+ v in- sw1 c s c s a a b v ref sw2 control logic capacitive dac capacitive dac comparator b figure 3. adc acquisition phase when the adc starts a conversion (figure 4), sw3 will open and sw1 and sw2 will move to position b, causing the comparator to become unbalanced. both inputs are disconnected once the conversion begins. the control logic and the charge redistribution dacs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a bal- anced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adcs output code. the output impedances of the sources driving the v in+ and the v in- pins must be matched otherwise the two inputs will have different set- tling times, resulting in errors. sw3 v in+ v in- sw1 c s c s a b a b v ref sw2 control logic capacitive dac capacitive dac comparator figure 4. adc conversion phase adc transfer function the output coding for the ad7450 is twos complement. the designed code transitions occur at successive lsb values (i.e. 1lsb, 2lsbs, etc.) and the lsb size is 2xv ref /4096. the ideal transfer characteristic of the ad7450 is shown in figure 5.
rev. prj preliminary technical data C12C ad7450 100...000 +v ref -1lsb 100...001 100...010 111...111 000...000 000...001 011...110 011...111 -v ref +1lsb 0lsb a d c c o d e 1lsb = 2xv ref /4096 analog input (v in+ -v in- ) figure 5. ad7450 ideal transfer characteristic typical connection diagram figure 6 shows a typical connection diagram for the ad7450 for both 5 v and 3 v supplies. in this setup the gnd pin is connected to the analog ground plane of the system. the v ref pin is connected to either a 2.5 v or a 1.25 v decoupled reference source depending on the power supply, to set up the analog input range. the com- mon mode voltage has to be set up externally and is the value that the two inputs are centered on. for more details on driving the differential inputs and setting up the com- mon mode, see the driving differential inputs section. the conversion result for the adc is output in a 16-bit word consisting of four leading zeros followed by the msb of the 12-bit result. for applications where power consumption is of concern, the power-down mode should be used between conversions or bursts of several conver- sions to improve power performance. see modes of operation section. cm* cm* * cm - common mode voltage v in+ v in- v dd sclk sdata c s gnd v ref c/p serial interface +3v/+5v supply 1.25v/2.5v vref 0.1f 0.1f 10f ad7450 v ref p-to-p v ref p-to-p figure 6. typical connection diagram the analog input the analog input of the ad7450 is fully differential. dif- ferential signals have a number of benefits over single ended signals including noise immunity based on the devices common mode rejection, improvements in distor- tion performance, doubling of the devices available dynamic range and flexibility in input ranges and bias points. figure 7 defines the fully differential analog input of the ad7450. v in+ ad7450 v in- v ref p-to-p v ref p-to-p common mode vo ltag e figure 7. differential input definition the amplitude of the differential signal is the difference between the signals applied to the v in+ and v in- pins (i.e. v in+ - v in- ). v in+ and v in- are simultaneously driven by two signals each of amplitude v ref that are 180 out of phase. the amplitude of the differential signal is therefore -v ref to +v ref peak-to-peak (i.e. 2 x v ref ). this is re- gardless of the common mode (cm). the common mode is the average of the two signals, i.e. (v in+ + v in- )/2 and is therefore the voltage that the two inputs are centered on. this results in the span of each input being cm v ref /2. this voltage has to be set up externally and its range var- ies with v ref . as the value of v ref increases, the common mode range decreases. when driving the inputs with an amplfier, the actual common mode range will be determined by the amplifiers output voltage swing. figure 8 shows how the common mode range varies with v ref for a 5 v power supply and figure 9 shows an ex- ample of the common mode range when using the ad8138 differential amplifer to drive the analog inputs. the common mode must be in this range to guarantee the specifications. with a 3v power supply, the common mode range is tbd. for ease of use, the common mode can be set up to be equal to v ref , resulting in the differential signal being v ref centered on v ref . when a conversion takes place, the common mode is rejected resulting in a virtually noise free signal of amplitude -v ref to +v ref corresponding to he digital codes of 0 to 4095.
rev. prj preliminary technical data C13C ad7450 title 0 0 0 00 0 t it l e 0000 figure 8. input common mode range (cm) versus v ref (vdd = 5v and v ref (max) = 2.5v) -1 0 1 2 3 4 5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 vref common mode ran g e 2.8 0.9 figure 9. input common mode range versus v ref (vdd = 5v and v ref (max) = 2.5v) when driving v in+ and v in- with the ad8138 differential amplifier figure 10 shows examples of the inputs to v in+ and v in- for different values of v ref for v dd = 5 v. it also gives the maximum and minimum common mode voltages for each reference value according to figure 8. reference = 0.625 v (v ref max/4) 0.625 v peak to peak common mode (cm) cm min =0.275v cm max =3.8v reference = 1.25 v (v ref max/2) 1.25 v peak to peak common mode (cm) cm min =0.85v cm max =3.55v reference = 2.5 v (v ref max) 2.5 v peak to peak common mode (cm) cm min =2v cm max =3v figure 10. examples of the analog inputs to v in+ and v in- for different values of v ref for v dd = 5 v. analog input structure figure 11 shows the equivalent circuit of the analog input structure of the ad7450. the four diodes provide esd protection for the analog inputs. care must be taken to ensure that the analog input signals never exceed the sup- ply rails by more than 200mv. this will cause these diodes to become forward biased and start conducting into the substrate. these diodes can conduct up to 10ma with- out causing irreversible damage to the part. the capacitors c1, in figure 11 are typically 4pf and can primarily be attributed to pin capacitance. the resistors are lumped components made up of the on-resistance of the switches. the value of these resistors is typically about 100 v . the capacitors, c2, are the adcs sampling ca- pacitors and have a capacitance of 16pf typically. for ac applications, removing high frequency components from the analog input signal is recommended by the use of an rc low-pass filter on the relevant analog input pins. in applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the opamp will be a function of the particu- lar application.
rev. prj preliminary technical data C14C ad7450 v dd c1 d d v in+ r1 c2 v in- r1 c2 v dd d d c1 figure 11. equivalent analog input circuit. conversion phase - switches open track phase - switches closed when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases and performance will degrade. figure 12 shows a graph of the thd versus analog input signal frequency for dif- ferent source impedances. title 0 0 0 00 0 t it l e 0000 figure 12.thd vs analog input frequency for various source impedances tbd figure 13 shows a graph of thd versus analog input frequency for v dd of 5v and 3v, while sampling at 1mhz and 833khz with a sclk of 18 mhz and 15mhz respectively. title 0 0 0 0 0 0 t it l e 0000 figure 13.thd vs analog input frequency for 3v and 5v supply voltages tbd driving differential inputs differential operation requires that v in+ and v in- be si- multaneously driven with two equal signals that are 180 o out of phase. the common mode must be set up exter- nally and has a range which is determined by v ref , the power supply and the particular amplifier used to drive the analog inputs (see figure 8). differential modes of opera- tion with either an ac or dc input, provide the best thd performance over a wide frequency range. since not all applications have a signal preconditioned for differential operation, there is often a need to perform single ended to differential conversion. differential amplifier an ideal method of applying dc differential drive to the ad7450 is to use a differential amplifier such as the ad8138. this part can be used as a single ended to differential amplifier or as a differential to differential amplifier. in both cases the analog input needs to be bipolar. it also provides common mode level shifting and buffering of the bipolar input signal. figure 14 shows how the ad8138 can be used as a single ended to differential amplifier. the positive and negative outputs of the ad8138 are connected to the respec- tive inputs on the adc via a pair of series resistors to minimize the effects of switched capacitance on the front end of the adc. the rc low pass filter on each analog input is recommended in ac applications to remove high frequency components of the analog input. the architecture of the ad8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. if the analog input source being used has no impedance then all four resistors (rg1, rg2, rf1, rf2) should be the same. if the source has a 50 v impedance and a 50 v termination for example, the value of rg2 should be increased by 25 v to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain (see figure 14). the outputs of the amplifier are perfectly matched, balanced differential outputs of identical amplitude and are exactly 180 o out of phase.
rev. prj preliminary technical data C15C ad7450 the ad8138 is specified with 3 v, 5 v and 5 v power supplies but the best results are obtained when it is supplied by 5 v. a lower cost device that could also be used in this configuration with slight differences in characteristics to the ad8138 but with similar performance and operation is the ad8132. 2.5v 3.75v 1.25v rs* rs* rf2 2.5v 3.75v 1.25v external v ref (2.5v) v ref v in+ ad7450 v in- ad8138 c* c* *mount as close to the ad 7450 as possible and ensure high precision rs and cs are used rs - 10r; c - 1nf; rg1=rf1=rf2= 499r; rg2 = 5 23r rf1 rg1 v ocm 51r rg2 . gnd +2.5v -2.5v figure 14. using the ad8138 as a single ended to differen- tial amplifier opamp pair an opamp pair can be used to directly couple a differential signal to the ad7450. the circuit configurations shown in figures 15(a) and 15(b) show how a dual opamp can be used to convert a single ended signal into a differential signal for both a bipolar and a unipolar input signal re- spectively. the voltage applied to point a is the common mode voltage. in both diagrams, it is connected in some way to the reference but any value in the common mode range can be input here to setup the common mode. examples of suitable dual opamps that could be used in this configura- tion to provide differential drive to the ad7450 are the ad8042, ad8056 and the ad8022. care must be taken when chosing the opamp used, as the selection will depend on the required power supply and the system performance objectives. the driver circuits in fig- ures 15(a) and 15(b) are optimized for dc coupling applications requiring optimum distortion performance. the differential op-amp driver circuit in figure 15(a) is configured to convert and level shift a 2.5 v p-p single ended, ground referenced (bipolar) signal to a 5 v p-p differential signal centered at the v ref level of the adc. the circuit configuration shown in figure 15(b) converts a unipolar, single ended signal into a differential signal. gnd v ref p-to-p 27 27 390 220 220 10k external v ref 220 v dd v+ v+ v- v- v in+ v in- v ref ad7450 220 20k . 0.1f . . a figure 15(a). dual opamp circuit to convert a single ended bipolar input into a differential input gnd v ref p-to-p 27 27 390 220 10k external v ref 220 v dd v+ v+ v- v- v in+ v in- v ref ad7450 220 . . 0.1f a vref/2 figure 15(b). dual opamp circuit to convert a single ended unipolar input into a differential input rf transformer in systems that do not need to be dc-coupled, an rf trans- former with a center tap offers a good solution for generating differential inputs. figure 16 shows how a transformer is used for single ended to differential conver- sion. it provides the benefits of operating the adc in the differential mode without contributing additional noise and distortion. an rf transformer also has the benefit of providing electrical isolation between the signal source and the adc. a transformer can be used for most ac ap- plications. the center tap is used to shift the differential signal to the common mode level required, in this case it is connected to the reference so the common mode level is the value of the reference.
rev. prj preliminary technical data C16C ad7450 c external v ref (2.5v) r r r v ref v in+ ad7450 v in- 2.5v 3.75v 1.25v 2.5v 3.75v 1.25v figure 16. using an rf transformer to generate differential inputs reference section an external reference source is required to supply the reference to the ad7450. this reference input can range from 100 mv to 2.5 v. with a 5v power supply, the specified and maximum reference is 2.5v. with a 3v power supply, the specified reference is 1.25v and the maximum reference is 2.2v. in both cases, the reference is functional from 100mv. it is important to note that as the reference input moves closer to the maximum reference input, the performance improves. when operating the device from v dd = 2.7v to 3.3v, the maximum analog input range (vinmax) must never be greater than v dd + 0.3v to comply with the maximum ratings of the device. for example: vinmax = v dd + 0.3 vinmax = v ref + v ref /2 if v dd = 3.3v then vinmax = 3.6 v therefore 3xv ref /2 = 3.6 v v ref max = 2.4 v therefore, when operating at v dd = 3.3 v, the value of v ref can range from 100mv to a maximum value of 2.4v. when v dd = 2.7 v, v ref max = 2 v. when operating from v dd = 4.75 v to 5.25 v, there is no need to worry about the maximum analog input in relation to v dd as the maximum v ref is 2.5 v resulting the maximum analog input span being 3.75 v which is not close to v dd . the performance of the part at different reference values is shown in tpc9 to tpc13 and in tpc16 and tpc17. the value of the reference sets the analog input span and the common mode voltage range. errors in the reference source will result in gain errors in the ad7450 transfer function and will add to specified full scale errors on the part. a capacitor of 0.1f should be used to decouple the v ref pin to gnd. table i lists examples of suitable volt- age references that could be used that are available from analog devices and figure 17 shows a typical connection diagram for the v ref pin. table i examples of suitable voltage references reference output initial operating voltage accuracy current (% max) ( a) ad589 1.235 1.2-2.8 50 ad1580 1.225 0.08-0.8 50 ref192 2.5 0.08-0.4 45 ref43 2.5 0.06-0.1 600 ad780 2.5 0.04-0.2 1000 v ref ad7450* v dd 1 2 3 4 5 6 7 8 vin temp gnd tri m vout opsel 0.1f nc nc nc nc vdd 0.1f 0.1f 10nf *additiona l pins omitted for clarity ad780 figure 17. typical v ref connection diagram single ended operation when supplied with a 5 v power supply, the ad7450 can handle a single ended input. the design of this part is optimized for differential operation so with a single ended input performance will degrade. linearity will degrade by typically 0.2lsbs, zero code and the full scale errors will degrade by typically 2lsbs and ac performance is not guaranteed. to operate the ad7450 in single ended mode, the v in+ input is coupled to the signal source while the v in- input is biased to the appropriate voltage corresponding to the mid-scale code transition. this voltage is the common mode, which is a fixed dc voltage (usually the reference). the v in+ input swings around this value and should have voltage span of 2 x v ref to make use of the full dynamic range of the part. the input signal will therefore have peak to peak values of common mode v ref . if the analog input is unipolar then an opamp in a non-inverting unity gain configuration can be used to drive the v in+ pin. because the adc operates from a single supply, it will be necessary to level shift ground based bipolar signals to comply with the input requirements. an opamp can be configured to rescale and level shift the ground based bi- polar signal so it is compatible with the selected input range of the ad7450 (see figure 18).
rev. prj preliminary technical data C17C ad7450 figure 19. serial interface timing diagram 1 2345 13 16 1514 t 3 0 0 0 0 db11 db10 db2 db1 db0 t 2 4 leading zeros 3-state t 4 t 6 t 5 t 7 t 8 t quiet convert t b cs sclk s data t 1 external v ref (2.5v) v in 0v +2.5v -2.5v 0.1f v ref v in+ ad7450 v in- r r r r 0v +2.5v +5v figure 18. applying a bipolar single ended input to the ad7450 serial interface figure 19 shows a detailed timing diagram for the serial interface of the ad7450. the serial clock provides the conversion clock and also controls the transfer of data from the ad7450 during conversion. cs initiates the conversion process and frames the data transfer. the fall- ing edge of cs puts the track and hold into hold mode and takes the bus out of three-state. the analog input is sampled and the conversion initiated at this point. the conversion will require 16 sclk cycles to complete. once 13 sclk falling edges have occurred, the track and hold will go back into track on the next sclk rising edge as shown at point b in figure 19. on the 16th sclk falling edge the sdata line will go back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, the conversion will be terminated and the sdata line will go back into three-state on the 16th sclk falling edge. 16 serial clock cycles are required to perform a conversion and to access data from the ad7450. cs going low provides the first leading zero to be read in by the micro- controller or dsp. the remaining data is then clocked out on the subsequent sclk falling edges beginning with the second leading zero. thus the first falling clock edge on the serial clock provides the second leading zero. the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. in applications with a slower sclk, it may be possible to read in data on each sclk rising edge i.e. the first rising edge of sclk after the cs falling edge would have the leading zero provided and the 15th sclk edge would have db0 provided. timing example 1 having f sclk = 18mhz and a throughput rate of 1msps gives a cycle time of: 1/throughput = 1/1000000 = 1s a cycle consists of: t 2 + 12.5 (1/f sclk ) + t acq = 1s. therefore if t 2 = 10ns then: 10ns + 12.5(1/18mhz) + t acq = 1s t acq = 296ns this 296ns satisfies the requirement of 275ns for t acq . from figure 20, t acq comprises of: 2.5(1/f sclk ) + t 8 + t quiet where t 8 = 45ns. this allows a value of 113ns for t quiet satisfying the minimum requirement of 100ns. timing example 2 having f sclk = 5mhz and a throughput rate of 315ksps gives a cycle time of : 1/throughput = 1/315000 = 3.174s a cycle consists of: t 2 + 12.5 (1/f sclk ) + t acq = 3.174s. therefore if t 2 is 10ns then: 10ns + 12.5(1/5mhz) + t acq = 3.174s t acq = 664ns
rev. prj preliminary technical data C18C ad7450 figure 20. serial interface timing example 1 2345 13 16 15 14 t 2 t 6 t 5 t 8 t quiet convert t b cs t acquisition 12.5(1/f sclk ) 1/throughput 10ns sclk c this 664ns satisfies the requirement of 275ns for t acq . from figure 20, t acq comprises of: 2.5(1/f sclk ) + t 8 + t quiet where t 8 = 45ns. this allows a value of 119ns for t quiet satisfying the minimum requirement of 100ns. as in this example and with other slower clock values, the signal may already be acquired before the conversion is complete but it is still necessary to leave 100ns minimum t quiet between conversions. in example 2 the signal should be fully acquired at approximately point c in figure 20. modes of operation the mode of operation of the ad7450 is selected by controlling the logic state of the cs signal during a conversion. there are two possible modes of operation, normal mode and power-down mode. the point at which cs is pulled high after the conversion has been initiated will determine whether or not the ad7450 will enter the power- down mode. similarly, if already in power-down, cs controls whether the device will return to normal operation or remain in power-down. these modes of operation are designed to provide flexible power management options. these options can be chosen to optimize the power dissipa- tion/throughput rate ratio for differing application requirements. normal mode this mode is intended for fastest throughput rate perfor- mance. the user does not have to worry about any power-up times as the ad7450 is kept fully powered up. figure 21 shows the general diagram of the operation of the ad7450 in this mode. the conversion is initiated on the falling edge of cs as described in the serial interface section. to ensure the part remains fully powered up, cs must remain low until at least 10 sclk falling edges have elapsed after the falling edge of cs . if cs is brought high any time after the 10th sclk fall- ing edge, but before the 16th sclk falling edge, the part will remain powered up but the conversion will be termi- nated and sdata will go back into three-state. sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. cs may idle high until the next conversion or may idle low until sometime prior to the next conversion. once a data transfer is complete, i.e. when sdata has returned to three-state, another conversion can be initiated after the quiet time, t quiet has elapsed by again bringing cs low. 4 leading zeros + conversion result sdata 10 16 c s sclk 1 figure 21. normal mode operation power down mode this mode is intended for use in applications where slower throughput rates are required; either the adc is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the adc is then powered down for a relatively long duration between these bursts of several conversions. when the ad7450 is in the power down mode, all analog circuitry is powered down. to enter power down mode, the conversion process must be interrupted by bringing cs high anywhere after the second falling edge of sclk and before the tenth falling edge of sclk as shown in figure 22. once cs has been brought high in this window of sclks, the part will enter power down and the conver- sion that was initiated by the falling edge of cs will be terminated and sdata will go back into three-state. the time from the rising edge of cs to sdata three- state enabled will never be greater than t 8 (see the timing specifications). if cs is brought high before the second sclk falling edge, the part will remain in normal mode and will not power-down. this will avoid accidental power-down due to glitches on the cs line.
rev. prj preliminary technical data C19C ad7450 figure 23. exiting power down mode sdata cs invalid data sclk 116 valid data 1 a the part begins to power up the part is fully powered up with vin fully acquired 10 10 16 t powerup in order to exit this mode of operation and power the ad7450 up again, a dummy conversion is performed. on the falling edge of cs the device will begin to power up, and will continue to power up as long as cs is held low until after the falling edge of the 10th sclk. the device will be fully powered up after 1sec has elapsed and, as shown in figure 23, valid data will result from the next conversion. if cs is brought high before the 10th falling edge of sclk, the ad7450 will again go back into power-down. this avoids accidental power-up due to glitches on the cs line or an inadvertent burst of eight sclk cycles while cs is low. so although the device may begin to power up on the falling edge of cs , it will again power-down on the rising edge of cs as long as it occurs before the 10th sclk falling edge. cs three state sclk sdata 12 10 figure 22. entering power down mode power up time the power up time of the ad7450 is typically 1sec, which means that with any frequency of sclk up to 18mhz, one dummy cycle will always be sufficient to allow the device to power-up. once the dummy cycle is complete, the adc will be fully powered up and the input signal will be acquired properly. the quiet time t quiet must still be allowed from the point at which the bus goes back into three-state after the dummy conversion, to the next falling edge of cs . when running at the maximum throughput rate of 1msps, the ad7450 will power up and acquire a signal within 0.5lsb in one dummy cycle, i.e. 1s. when powering up from the power-down mode with a dummy cycle, as in figure 23, the track and hold, which was in hold mode while the part was powered down, returns to track mode after the first sclk edge the part receives after the falling edge of cs . this is shown as point a in figure 23. although at any sclk frequency one dummy cycle is sufficient to power the device up and acquire v in , it does not necessarily mean that a full dummy cycle of 16 sclks must always elapse to power up the device and acquire v in fully; 1s will be sufficient to power the de- vice up and acquire the input signal. for example, if a 5mhz sclk frequency was applied to the adc, the cycle time would be 3.2s (i.e. 1/(5mhz) x 16). in one dummy cycle, 3.2s, the part would be powered up and v in acquired fully. however after 1s with a 5mhz sclk only 5 sclk cycles would have elapsed. at this stage, the adc would be fully powered up and the signal acquired. so, in this case the cs can be brought high after the 10th sclk falling edge and brought low again after a time t quiet to initiate the con- version. when power supplies are first applied to the ad7450, the adc may either power up in the power-down mode or normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. likewise, if the user wishes the part to power up in power-down mode, then the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as that shown in figure 22. once supplies are applied to the ad7450, the power up time is the same as that when powering up from the power-down mode. it takes approximately 1s to power up fully if the part powers up in normal mode. it is not necessary to wait 1s before executing a dummy cycle to ensure the desired mode of operation. instead, the dummy cycle can occur directly after power is supplied to the adc. if the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been al- lowed. as mentioned earlier, when powering up from the power- down mode, the part will return to track upon the first sclk edge applied after the falling edge of cs . how- ever, when the adc powers up initially after supplies are applied, the track and hold will already be in track. this means if (assuming one has the facility to monitor the adc supply current) the adc powers up in the desired mode of operation and thus a dummy cycle is not re-
rev. prj preliminary technical data C20C ad7450 quired to change mode, then neither is a dummy cycle required to place the track and hold into track. power versus throughput rate by using the power-down mode on the ad7450 when not converting, the average power consumption of the adc decreases at lower throughput rates. figure 24 shows how, as the throughput rate is reduced, the device remains in its power-down state longer and the average power con- sumption reduces accordingly. it shows this for both 5v and 3v power supplies. for example, if the ad7450 is operated in continous sam- pling mode with a throughput rate of 100ksps and an sclk of 18mhz and the device is placed in the power down mode between conversions, then the power con- sumption is calculated as follows: power dissipation during normal operation = 13mw max (for v dd = 5v). if the power up time is 1 dummy cycle i.e. 1sec, and the remaining conversion time is another cycle i.e. 1sec, then the ad7450 can be said to dissipate 13mw for 2sec* during each conversion cycle. if the throughput rate = 100ksps then the cycle time = 10sec and the average power dissipated during each cycle is: (2/10) x 13mw = 2.6mw for the same scenario, if v dd = 3v, the power dissipation during normal operation is 6mw max. the ad7450 can now be said to dissipate 6mw for 2sec* during each conversion cycle. the average power dissipated during each cycle with a throughput rate of 100ksps is therefore: (2/10) x 6mw = 1.2mw this is how the power numbers in figure 24 are calcu- lated. for throughput rates above 320ksps, it is recommended that for optimum power performance, the serial clock fre- quency is reduced. *this figure assumes a very small time used to enter the power down mode. this will increase as the burst of clocks used to enter the power down mode is increased. 0 50 100 150 200 250 300 350 throughput (ksps) power (mw) vdd = 5v sclk = 18mhz vdd = 3v sclk = 15mhz 0.01 0.1 1 10 100 figure 24. ad7450 power versus throughput rate for power down mode
rev. prj preliminary technical data C21C ad7450 microprocessor and dsp interfacing the serial interface on the ad7450 allows the part to be directly connected to a range of different microproces- sors. this section explains how to interface the ad7450 with some of the more common microcontroller and dsp serial interface protocols. ad7450 to adsp21xx the adsp21xx family of dsps are interfaced directly to the ad7450 without any glue logic required. the sport control register should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right justify data slen = 1111, 16-bit data words isclk = 1, internal serial clock tfsr = rfsr = 1, frame every word irfs = 0, itfs = 1. to implement the power-down mode slen should be set to 1001 to issue an 8-bit sclk burst. the connection diagram is shown in figure 25. the adsp21xx has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode and the sport control register is set up as described. the frame synchronisation signal generated on the tfs is tied to cs and as with all signal processing applications equidistant sampling is necessary. however, in this ex- ample, the timer interrupt is used to control the sampling rate of the adc and under certain conditions, equidistant sampling may not be acheived. . ad7450* sclk sdata cs sclk dr rfs tfs adsp21xx* *additional pins omitted for clarity figure 25. interfacing to the adsp 21xx ad7450 to tms320c5x/c54x the serial interface on the tms320c5x/c54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the ad7450. the cs input allows easy interfacing between the tms320c5x/c54x and the ad7450 without any glue logic required. the serial port of the tms320c5x/c54x is set up to operate in burst mode with internal clkx (tx serial clock) and fsx (tx frame sync). the serial port control register (spc) must have the following setup: fo = 0, fsm = 1, mcm = 1 and txm = 1. the format bit, fo, may be set to 1 to set the word length to 8-bits, in order to implement the power-down mode on the ad7450. the connection dia- gram is shown in figure 26. it should be noted that for signal processing applications, it is imperative that the frame synchronisation signal from the tms320c5x/c54x will provide equidistant sampling. ad7450* sclk sdata cs clkx fsr tms320c5x/c54x* *additional pins omitted for clarity clkr dr fsx figure 26. interfacing to the tms320c5x/c54x the timer registers etc., are loaded with a value which will provide an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to con- trol the rfs and hence the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given, (i.e. ax0=tx0), the state of the sclk is checked. the dsp will wait until the sclk has gone high, low and high before transmission will start. if the timer and sclk val- ues are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, then the data may be transmitted or it may wait until the next clock edge. for example, the adsp-2111 has a master clock fre- quency of 16mhz. if the sclkdiv register is loaded with the value 3 then a sclk of 2mhz is obtained, and 8 master clock periods will elapse for every 1 sclk period. if the timer registers are loaded with the value 803, then 100.5 sclks will occur between interrupts and subse- quently between transmit instructions. this situation will result in non-equidistant sampling as the transmit instruc- tion is occuring on a sclk edge. if the number of sclks between interrupts is a whole integer figure of n then equidistant sampling will be implemented by the dsp. ad7450 to mc68hc16 the serial peripheral interface (spi) on the mc68hc16 is configured for master mode (mstr = 1), clock polar- ity bit (cpol) = 1 and the clock phase bit (cpha) = 0. the spi is configured by writing to the spi control reg- ister (spcr) - see 68hc16 user manual. the serial transfer will take place as a 16-bit operation when the size bit in the spcr register is set to size = 1. to implement the power-down modes with an 8-bit transfer set size = 0. a connection diagram is shown in figure 27.
rev. prj preliminary technical data C22C ad7450 ad7450* sdata cs * *additional pins omitted for clarity miso/pmc0 sclk /pmc2 sclk ss/pmc3 mc68hc16* figure 27. interfacing to the mc68hc16 ad7450 to dsp56xxx the connection diagram in figure 28 shows how the ad7450 can be connected to the ssi (synchronous serial interface) of the dsp56xxx family of dsps from motorola. the ssi is operated in synchronous mode (syn bit in crb =1) with internally generated 1-bit clock period frame sync for both tx and rx (bits fsl1 =1 and fsl0 =0 in crb). set the word length to 16 by setting bits wl1 =1 and wl0 = 0 in cra. to implement the power-down mode on the ad7450 then the word length can be changed to 8 bits by setting bits wl1 = 0 and wl0 = 0 in cra. it should be noted that for signal processing applications, it is imperative that the frame synchronisation signal from the dsp56xxx will provideequidistant sampling. ad7450* sdata cs * *additional pins omitted for clarity srd sclk sclk sr2 dsp56xxx* figure 28. interfacing to the dsp56xx
rev. prj preliminary technical data C23C ad7450 application hints grounding and layout the printed circuit board that houses the ad7450 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily sepa- rated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined in only one place and the connection should be a star ground point estab- lished as close to the gnd pin on the ad7450 as possible. avoid running digital lines under the device as this will couple noise onto the die. the analog ground plane should be allowed to run under the ad7450 to avoid noise coupling. the power supply lines to the ad7450 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and analog sig- nals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double- sided board. in this technique the component side of the board is dedi- cated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10f tantalum capacitors in parallel with 0.1f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device. evaluating the ad7450 performance the recommended layout for the ad7450 is outlined in the evaluation board for the ad7450. the evaluation board package includes a fully assembled and tested evalu- ation board, documentation and software for controlling the board from a pc via the evaluation board controller. the evaluation board con- troller can be used in conjunction with the ad7450 evaluation board, as well as many other analog devices evaluation boards ending with the cb designator, to dem- onstrate/evaluate the ac and dc performance of the ad7450. the software allows the user the perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7450.
rev. prj preliminary technical data C24C ad7450 0.1968 (5.00) 0.1890 (4.80) 85 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating pl ane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1 .27 ) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0 .0 196 (0.5 0) 0 .0 099 (0.2 5) x45 8-lead soic (so-8) outline dimensions dimensions shown in inches and (mm). 8-lead microsoic (rm-8) 8 5 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122(3.10) 0.114(2.90) seating pl an e 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 27 0.120 (3.05) 0.112 (2.84)

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